Toshiba leads 65nm CMOS process technology with lowest power consumption transistor for mobile products

Using a new gate dielectric material, Toshiba has developed a CMOS transistor that reduces gate leakage current to a level only 1/1000 that of CMOS transistors with conventional gate dielectrics.

The company replaced the usual silicon dioxide in the transistor gate dielectric with hafnium silicate oxide nitridenitrided hafnium silicate (HfSiON), a high dielectric constant (high-k) material, and confirmed its performance.

"We now plan to apply the new process to the mass production of system LSIs for mobile products in 2005," said Ahmed Khalil, regional manager of the Toshiba's Middle East computer systems division.

Toshiba leads the semiconductor industry in the development of advanced process technology, including 90nm CMOS process technology for mass production of systems LSIs. Last December, Toshiba, with Sony Corporation, announced the development of the world's first 65-nanometer CMOS process technology for embedded DRAM system LSIs for high power consumption performance products.

"The announcement of a 65nm process technology suited to next generation mobile products, which must combine high-speed performance with low power consumption, confirms our continuing lead in essential technologies for advanced generations of system LSIs," added Khalil.

The gate dielectric in LSI grows progressively thinner with each new generation of CMOS process technology. However, that thinness can cause larger gate leakage current. This is emerging as a critical issue, especially in lower power products, such as mobile terminals, and it has spurred a search for thicker gate dielectric materials offering the same performance as SiO2. HfSiON, nitrided hafnium silicatehafnium silicate oxide nitride, is recognized as a promising material, but there are few reports of any practical fabrication process that can be applied to mass production.

Toshiba has developed a fabrication process for HfSiON gate dielectric film for 65 nm low power CMOS applications and confirmed its characteristic with an experimentally fabricated LSI with 50nm gate-length CMOS transistors.